 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| network access products ServiceSAR Controller RS8234 Full-Featured ATM xBR Service Segmentation and Reassembly Controller (ServiceSAR) Conexant's RS8234 accelerates service interworking by emphasizing performance under worst-case short packet conditions. In addition, the PCI host interface is one of the most efficient in the industry in terms of bus occupancy. The RS8234 not only meets the stringent requirements of T.M. 4.1, but also enables advanced traffic control functions such as GFR, CBR tunneling and virtual path shaping. The RS8234's service-specific features allow system designers to accelerate specific protocol interworking functions for applications like IP over ATM, Frame Relay or LAN emulation. The device's unique architecture enables advanced networklevel functionality and topologies. A few examples of these features include echo suppression of multicast data frames on ELAN channels, and peak cell rate (PCR) control established per VCC, per tunnel, and/or per scheduling priority. Distinguishing Features * Fully T.M. 4.1-compliant * 3.3V/5V low power utilization (< 1 watt) * PCI 2.1/UTOPIA Level 1 * Industrial temperature * 16 multiservice tunnels * 64K VCCs * 388-pin BGA network access products ServiceSAR Controller RS8234 Integrated Management The RS8234 complies with ATM Forum specifications UNI 3.1, T.M. 4.1 and all other relevent standards. The RS8234 provides integrated traffic management for all service categories, including constant bit rate (CBR), variable bit rate (VBR) (single- and dual-leaky bucket), real-time VBR, unspecified bit rate (UBR), available bit rate (ABR), guaranteed frame rate (GFR) (guaranteed MCR on UBR VCCs), and generic flow control (GFC). The xBR traffic management block automatically schedules each VCC according to user assigned-parameters to maximize line utilization. The RS8234 System The RS8234 consists of five separate coprocessors (incoming and outgoing DMA, segmentation, reassembly and xBR traffic manager), each of which maintains state information in shared, off-chip memory. This memory is controlled by the SAR through the local bus interface, which arbitrates access to the bus between the various coprocessors. These coprocessors, though they run off the same system clock, operate asynchronously from each other. Communication between the coprocessors takes place through on-chip FIFOs or through queues in local memory. Advanced Architecture The RS8234's architecture is designed to minimize and control host traffic congestion. The host manages the RS8234 terminal using write-only control and status queues. The control queues are also isolated from their associated data buffers via buffer descriptors, allowing the data buffers to hold payload data only. For example, the host submits data for transmit by writing buffer descriptor pointers to one of 32 transmit queues. These entries may be thought of as task lists for the ServiceSAR to perform. The 32 receive queues couple with the transmit structure to create complete host peers. The RS8234 enables control of traffic congestion through mechanisms like receive buffer memory limitations (called firewalls), and through explicit notification of congestion by the host. This architecture reduces the control burden on the host system while minimizing PCI bus utilization, by eliminating reads across the PCI bus from host control activities. It also provides control points to manage congestion, which is critical for ABR. The user sets the range of available transmission rates for the scheduler by setting the size of the dynamic schedule table and the duration of each scheduling slot in the table. The RS8234's on-chip coprocessor blocks are surrounded by high-performance PCI and UTOPIA ports for glueless interface to a variety of system components with full line-rate throughput and low bus occupancy. Figure 1 illustrates these functional blocks. xBR Cell Scheduler The cell scheduler rate-shapes all segmentation traffic according to per-channel parameters. The RS8234 supports eight user-assigned scheduling priorities in addition to CBR. The user assigns a priority to each channel. The user can further control consumption of bandwidth by assigning peak cell rate limits to four of those scheduling priorities. a software driver to the RS8234, on top of which a system designer can develop and place proprietary driver software. This interface allows users to easily port their applications to the RS8234EVM. This software is written in C, and source code is available under license agreement. RS8234HPI primitives are used by higher-level application software (such as network management and device drivers) to obtain ATM services as required by their upper protocol layers. These primitives handle SAR resource, control and status management. The RS823xHPI performs functions in the following categories: The RS8234EVM also includes documentation, a full set of design schematics, and artwork for the RS8234EVM PCI card. * RS8234 SAR device initialization * Memory resource allocation * Resource management RS823xHPI Hardware Programming Interface The RS8234 Hardware Programming Interface (HPI) provides a set of fully-defined software primitives to interface with an ATM UNI port based on the RS8234 SAR. It serves as an interface point for system software designed to configure and manage the RS8234-based UNI without the necessity of detailed manipulation of hardwarerelated structures. It thus provides a layer of abstraction from the hardware for the system designer and user. * Connection management (including VCC setup and teardown, and processing status) * Segmentation/data transmission * Data reception/reassembly * Statistics gathering/error reporting * Diagnostic testing Features Software reference design Modular software design Benefits Shortens development time of customer system-specific ATM applications. Allows users to utilize only those functions they want and to incorporate those functions into their own applications. Users can establish ABR, CBR, UBR or VBR connections at VCC setup on each of over 32,000 channels. Provides detailed examples for control and management of the RS8234. Significantly shortens design time. Enables users to easily port their application to the RS8234EVM. Gives users a clear description of how the software and hardware function. Offers a layer of abstraction for ease of use of the RS823xHPI primitives. Reference device driver for VxWorks. Dynamic rate control per virtual channel SAR initialization and VCC control Well-defined, robust RS823xHPI interface Well-documented C source code RS823xHPI macro layer software network access products RS8234 xBR SAR Special Features: Service-Specific Performance Accelerators * * * * LECID filtering and echo suppression Dual leaky bucket based on CLP (Frame Relay) Frame Relay DE interworking Internal SNMP MIB counters Flexible Architectures * Multi-peer host * Direct switch attachment via reverse UTOPIA * ATM Terminal - Host control - Local Bus control * Optional local processor The RS823xHPI provides a reference implementation of these critical functions in order to shorten the development of a production-quality, customer system-specific ATM application. The RS823xHPI is implemented in well-documented C source code, specifically written to be highly portable across a multiplicity of processors, compilers and development environments. xBR Traffic Management * T.M. 4.1 Service Classes - CBR - VBR (single, dual and CLP 0+1 leaky buckets) - Real-time VBR - ABR - UBR - GFC (controlled and uncontrolled flows) - Guaranteed frame rate (GFR) (guaranteed MCR on UBR VCCs) * 8 levels of priorities (8 + CBR) * Dynamic per-VCC scheduling * Multiple programmable ABR templates (supplied by Conexant or user) * Scheduler driven by local clock for low-jitter CBR * Internal RM OAM cell feedback path * Virtual FIFO rate matching (source rate matching) * Tunneling - VP tunnels (VCI interleaving on PDU boundaries) - CBR tunnels (cells interleaved on UBR with an aggregate CBR limit) RS8234EVM Evaluation Software The RS8234EVM system software is a complete reference implementation of an ATM terminal for device testing and evaluation using the RS8234EVM, RS823xHPI and the VxWorks operating system. This evaluation system software provides a reference design that the system designer can utilize in part or in full in tailoring customer-specific ATM applications. The RS823xHPI macro layer, together with the RS823xHPI, forms a complete device driver for the RS8234 in a VxWorks environment. The user does not need an advanced knowledge of the device or full understanding of every detail to successfully operate the RS8234 device. Multi-Queue Segmentation Processing * * * * * * * * * * * 32 transmit queues with optional priority levels 64K VCCs maximum ** AAL5 and AAL3/4 CPCS generation AAL0 null CPCS (optional use of PTI for PDU demarcation) ATM cell header generation Raw cell mode (52 octet) 200 Mbps half duplex 155 Mbps full duplex (with 2-cell PDUs) Message and streaming status modes Variable-length transmit FIFO-CDV-host latency matching (1 to 9 cells) Symmetric Tx and Rx architecture - Buffer descriptors - Queues User-defined field circulates back to host (32 bits) Distributed host or SAR-shared memory segmentation Simultaneous segmentation and reassembly Per-PDU control of CLP/PTI (UBR) Per-PDU control of AAL5 UU field Virtual Tx FIFO (PCI host) Also provided is the traffic generator and checker (TGC), which utilizes the RS823xHPI primitives to send ATM traffic and check the data on its return on the reassembly side. This module was designed to exercise the functionality of the RS8234 device. * * * * * * ABR Traffic Management The ABR flow control manager dynamically rateshapes ABR traffic independently per VCC, based upon network feedback. One or more ABR templates are used to govern the behavior of traffic. Both relative rate (RR) and explicit rate (ER) algorithms are employed when computing a rate adjustment on an ABR VCC. Programmable ABR templates allow rate-shaping policies on groups of VCCs to be tuned for different network applications. The RS8234 automatically generates and processes all resource management (RM) cells. The on-chip hardware, coupled with the user-defined ABR templates, implements all required source and destination behaviors as defined in T.M. 4.1. Optional behaviors such as use-it-or-lose-it, out-of-rate RM cells, host congestion and allowed cell rate (ACR) monitoring are also supported. Early Packet Discard for Frame Relay and LAN Emulation The early packet discard (EPD) feature provides a mechanism to discard complete or partial CPCSPDUs based upon service discard attributes or error conditions. For example, the reassembly coprocessor performs EPD functions for the following conditions: Frame Relay packet discard based on the discard eligibility (DE) field in the received frame and the channel exceeding a user-defined priority threshold; LANE-LECID packet discard to implement echo suppression on multicast data frames on ELAN channels; and for errors like receive FIFO full condition/threshold and various AAL3/4 MIB errors. Figure 1. RS8234 functional block diagram network access products IP and Frame Relay Interworking The VBR-3, CLPO+1 category includes rate-shaping via the dual leaky bucket GCRA algorithm based on the CLP bit which is used in Frame Relay applications and is recommended by the IETF for use with IP . CBR Tunneling The user can delineate up to four CBR pipes (or tunnels) in which to transmit multiple channels. The tunneled VCCs can be further shaped as UBR, VBR or ABR connections. UNI or NNI Addressing The RS8234 handles both UNI (8-bit VPI field) and NNI (12-bit VPI field) addresses. RS8234EVM (Evaluation Module) This PCI card is specifically designed to be a fullfeatured ATM controller based on the RS8250 ATM receiver/transmitter and the RS8234 ServiceSAR. Virtual Path Networking The RS8234 can interleave segmentation of numerous VCCs (i.e., separate VC channels) as members of one VP VP-based traffic shaping . is supported. The entire VP is scheduled according to one set of traffic parameters. The PHY interface comes configured with an optical OC-3 connection for testing at 155 Mbps. The PCI interface between the host processor and the local system is controlled by the RS8234 Hardware Programming Interface (RS823xHPI), Conexant-Furnished Evaluation Software Module Typical User Application PCI Bus Port Figure 2. RS8234EVM system software What is ATM? Multi-Queue Reassembly Processing * * * * 32 reassembly queues 64K VCCs maximum ** AAL5 and AAL3/4 CPCS checking AAL0 - PTI termination - Cell count termination Early packet discard, based on: - Receive buffer underflow - Receive status overflow - CLP with priority threshold - AAL5 max PDU length - Rx FIFO full - Frame Relay DE with priority threshold - LECID filtering for echo suppression - Per-VCC firewalls Dynamic channel lookup (NNI or UNI addressing) - Supports full address space - Deterministic - Flexible VCI count per VPI - Optimized for signaling address assignment Message and streaming status modes Raw cell mode (52 octet) 200 Mbps half duplex 155 Mbps full duplex (with 2-cell PDUs) Distributed host or SAR shared memory reassembly 8 programmable reassembly hardware time-outs (assignable per VCC ) Global max PDU length for AAL5 Per-VCC buffer firewall (memory usage limit) Simultaneous reassembly and segmentation Idle cell filtering 32K duplex VCCs Standards-Based I/O * 33 MHz PCI 2.1 * Serial EEPROM to store PCI configuration information * PHY Interfaces - UTOPIA master (Level 1) - UTOPIA slave (Level 1) * Flexible SAR-shared memory architecture * Optional local control interface * Boundary scan for board-level testing * Source loopback, for diagnostics * Glueless connection to Conexant's RS8250 ATM PHY device Asynchronous Transfer Mode (ATM) has emerged as the primary networking technology for next-generation, multiservice communication networks. ATM-enabled services benefit the Internet as well as emerging applications in science, telemedicine and distance learning. Just as the Internet revolutionized worldwide communications, ATM brings new meaning to high-speed networking. * Electrical/Mechanical * * * * * * * * 388-pin BGA package 3.3V power supply 5V tolerant I/O pads 5V - 3.3V PCI pads Low power 1.0 W (typical) at full rate Industrial temperature range TTL level inputs CMOS level outputs * ATM, which uses a fixed-size packet, or cell, is a transport protocol capable of providing a homogeneous network for all traffic types, whether the application is to carry conventional telephony, video entertainment, or data traffic over LANs, MANs or WANs. * * * * * * * * * * * Standards Compliance UNI/NNI 3.1 T.M. 4.1 Bellcore GR-1248 ATM Forum B-ICI V 2.0 I.363 I.610 /GR-1248 AToM MIB (RFC1695) ILMI MIB ANSI T1.635 GFC per I.361 SNMP * I2C Protocol * PCI Revision 2.1 * IEEE 1149.1-1990 * IEEE 1149.1 supplement B, 1994 * * * * * * * * * * * The ITU-T and ANSI selected ATM for Broadband-ISDN. SONET/SDH, as specified by the ITU, is intended as the primary transport mechanism for ATM cells in WAN applications. ATM also plays a key role in next-generation consumer applications for high-speed Internet access and wireless access. The ADSL Forum and the Universal ADSL Working Group chose ATM as the network layer protocol for G.lite and G.DMT ADSL. High-Performance Host Architecture with Buffer Isolation * * * * * * * * * * * * * Write-only control and status Read multiple command for data transfer Up to 32 host clients control and status queues Physical or logical clients - Enables peer-to-peer architecture Descriptor-based buffer chaining Scatter/gather DMA Endian neutral Non-word (byte) aligned host buffer addresses Automatically detects presence of Tx data or Rx free buffers Virtual FIFOs (PCI bursts treated as single address) Hardware indication of BOM Allows isolation of system resources Status queue interrupt delay Statistics and Counters * Global register counter of # of cells transmitted * Global register counter of # of cells received on active channels * Global register counter of # of cells received on inactive channels * Global register counter of # of AAL5 CPCS-PDUs discarded due to per-channel firewall, etc * RSM per VCC service discard counters (Frame Relay and LANE) * 1 programmable interval timer (32 bits with interrupt) * Per-VCC AAL3/4 MIB counters: - # cells with CRC10 errors - # cells with MID errors - # cells with LI errors - # cells with SN errors - # cells with BOM or SSM errors - # cells with EOM errors ** Depends on local memory size and device configuration; 32K VCCs typically. ATM physical-layer (ATM-PHY) IC devices adapt ATM cells to and from transmission rates ranging from 1.544 Mbps to 2.4 Gbps, via a standard system interface called UTOPIA. ATM-PHY devices perform ATM cell functions (transmission convergence) such as cell scrambling/descrambling, cell delineation (HEC), cell header processing, and cell-rate decoupling as well as rate-specific functions for frame generation/recovery, frame adaptation and clock/data recovery. Designer Toolkit * Evaluation module (RS8234EVM) * Reference schematics * Hardware Programming Interface - RS8234HPI reference source code (C) Generous Implementation of OAM-PM Protocols * Detection of all F4/F5 OAM flows * Internal PM monitoring and generation for up to 128 VCCs * Optional global OAM Rx/Tx queues * In-line OAM insertion and generation features and specifications Product Features * AAL0, AAL5, AAL3/4 * Factory-supplied ABR templates (user may configure) * xBR Traffic Manager - CBR - VBR (single bucket) - VBR (dual bucket) - VBR (CLP 0+1) - rt-VBR - ABR (TM4.0) - UBR - GFC - GFR (guaranteed MCR on UBR VCCs) * 32K duplex VCCs (non ABR) * PCI 2.1 * UTOPIA Level 1 * Glueless RS8250 ATM PHY interface * Reference design available * RS8234 evaluation system available * Reference software available (RS823xHPI) Applications * ATM Uplinks - Routers - Ethernet switches * ATM Service Adapters - Frame Relay over ATM - IP over ATM - LAN emulation * ATM Servers - File servers - Control servers * LANE * MPOA * P-NNI * SIG Further Information literature@conexant.com (800) 854-8099 (North America) (949) 483-6996 (International) Order # 101095A 00-0683 Network Access Printed in USA Europe North - England Phone: +44 1344 486444 Fax: +44 1344 486555 Europe - Israel/Greece Phone: +972 9 9524000 Fax: +972 9 9573732 Europe South - France Phone: +33 1 41 44 36 51 Fax: +33 1 41 44 36 90 Europe Mediterranean - Italy Phone: +39 02 93179911 Fax: +39 02 93179913 Europe - Sweden Phone: +46 (0) 8 5091 4319 Fax: +46 (0) 8 590 041 10 Europe - Finland Phone: +358 (0) 9 85 666 435 Fax: +358 (0) 9 85 666 220 World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Newport Beach, CA 92660-3007 Phone: (949) 483-4600 Fax 1: (949) 483-4078 Fax 2: (949) 483-4391 Americas U.S. Northwest - Santa Clara Phone: (408) 249 -9696 Fax: (408) 249 -7113 U.S. Southwest - Los Angeles Phone: (805) 376 -0559 Fax: (805) 376 - 8180 U.S. Southwest - Newport Beach Phone: (949) 483-9119 Fax: (949) 483-9090 U.S. San Diego Phone: (858) 713-4730 Fax: (858) 713-4008 U.S. North Central - Illinois Phone: (630) 773-3454 Fax: (630) 773 -3907 U.S. South Central/Mexico - Texas Phone: (972) 871-1920 Fax: (972) 871- 8910 U.S. Northeast - Massachusetts Phone: (978) 367-3200 Fax: (978) 256 - 6868 U.S. Carolinas - North Carolina Phone: (919) 858 -9110 Fax: (919) 858 - 8669 U.S. Southeast/South America - Florida Phone: (727) 799 - 8406 Fax: (727) 799 - 8306 U.S. Mid-Atlantic - Pennsylvania Phone: (215) 244- 6784 Fax: (215) 244- 9292 Canada - Ontario Phone: (613) 271-2358 Fax: (613) 271-2359 Ordering Information Part Number RS8234EBGD RS8234/8250EVM Asia Pacific Taiwan Phone: (886 -2) 2-720-0282 Fax: (886 -2) 2-757- 6760 Australia Phone: (61-2) 9869 4088 Fax: (61-2) 9869 4077 China - Central Phone: 86 -21- 6361-2515 Fax: 86 -21- 6361-2516 China - South Phone: (852) 2 827- 0181 Fax: (852) 2 827- 6488 China - South (Satellite) Phone: (86) 755 -5182495 Fax: (86 ) 755 -5183024 China - North Phone: (86 -10) 8529 - 9777 Fax: (86 -10) 8529 - 9778 India Phone: (91-11) 692-4789 Fax: (91-11) 692 -4712 Korea Phone: (82-2) 565-2880 Fax: (82-2) 565-1440 Korea (Satellite) Phone: (82-53) 745-2880 Fax: (82-53) 745-1440 Singapore Phone: (65) 737 7355 Fax: (65) 737 9077 Japan Phone: (81-3) 5371 1520 Fax: (81-3) 5371 1501 Description ATM Enhanced xBR SAR PCI Card implementing the RS8234 SAR as a UNI port Includes: RS823xHPI and HPI Macro Layer software, RS8234EVM Schematics, Porting Guide and download instructions, RS823xHPI specification For more information contact: Applications Engineering Telephone: 1-800-228-2777 Fax: (619) 452-1249 Internet: Comm-BtATM@conexant.com Conexant and the Conexant symbol are trademarks of Conexant Systems, Inc. Europe Europe Central - Germany Phone: +49 89 829 -1320 Fax: +49 89 834-2734 www.conexant.com |
Price & Availability of RS8250EVM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |